Needs have arisen for so-called intelligent buildings, factory and campus installations to accommodate the transmission of data at various bit rates such as those shown in Table 1.
TABLE 1 ______________________________________ EXAMPLE OF BIT RATES BIT RATE APPLICATION ______________________________________ 1. kb/s Card Access Control Data Bus 2. kb/s HVAC Data Bus 19.2 kb/s RS-232C Personal Computer Network B = 64. kb/s PBX Digital Telephone/Data C = 16. kb/s BBX Data/Control B + D = 144. kb/s BBX and ISDN DS1 = 1.544 Mb/s Telephone/Data Trunk Line 2.5 Mb/s Arcnet LAN 10. Mb/s Ethernet LAN 16. Mb/s IBM Token Passing LAN ______________________________________
These various bit rates must be supported by a network in such installations because they interconnect the equipment that provides intelligence to the facility. A multiplexer-demultiplexer system is typically used in a network carrying data, which network must be able to support a wide range of bit rates, and to reconfigure quickly, and with minimum cost to accommodate such changes.
Three categories of multiplexer-demultiplexer systems are in common use. They are the synchronous, asynchronous, and asynchronous high speed over-sampling multiplexer-demultiplexer systems. Many variations are known but Table 2 summarizes the key features of some representative systems.
The multiplexer of a multiplexer-demultiplexer system is designed to combine a number of data signals present at the input channels by multiplex sampling the data signals and transmitting them as a serial bit stream. The demultiplexer extracts the samples from the bit stream and places them into the output channels that correspond to the input channels. The original data signals are then reconstructed and provided as the output signals.
TABLE 2 ______________________________________ MULTIPLEXER-DEMULTIPLEXER SYSTEMS MULTIPLEXER- DEMULTIPLEXER SYSTEMS KEY FEATURES ______________________________________ Synchronous 1. Clock frequency is supplied to the data signal source 2. Data signals have same bit rate 3. Data signals are in phase 4. Multiplex sampling is done synchronously Asynchronous 1. Data signal bit rate is lower than the specified operational bit rate 2. Bit-stuffing is used to match the data bit rate with the specified operational bit rate 3. Multiplex sampling is done synchronously Asynchronous 1. Multiplex sampling rate is more High Speed than 10 times higher than the Over-Sampling data signal bit rate 2. Data signals may have different bit rates and not be in phase 3. Multiplex sampling is done asynchronously ______________________________________
The input data signals to a synchronous multiplexer-demultiplexer system usually have the same bit rate and they are arranged to be all in phase at the input of the multiplexer. For this purpose, a single clock frequency supplied by the multiplexer-demultiplexer system is used to generate the data signals.
The data signals are then multiplex sampled sequentially and the sampled bits transmitted as a serial bit stream which is the TDM (Time Division Multiplex) signal.
The demultiplexer reverses the multiplex sampling operation by separating out each data sample, and delivering a reconstructed data to the output channel that corresponds to the input channel at the multiplexer.
For the asynchronous multiplexer-demultiplexer system, the bit rate of an input data signal to the multiplexer is usually slightly lower than the specified operational bit rate of the input channel of a synchronous multiplexer-demultiplexer system.
The bit rate of the data signal is adjusted to the specified operational bit rate by a bit-stuffing operation which inserts a sufficient number of dummy bits to bring the data signal bit rate into agreement with the specified operational bit rate. The data signal clock frequency and electronic circuits including a bit-stuffing circuit and a stuff-bit indicator circuit are used to realize this agreement of bit rates.
If the data signal clock frequency is not available, a clock recovery circuit is used to reproduce the frequency. In order to identify and remove the stuff-bits at the demultiplexer, means for identifying the stuff-bits are transmitted to the demultiplexer as part of the TDM bit stream.
At the demultiplexer, the synchronously transmitted data signal samples including the stuff-bits, are demultiplexed into the output channels corresponding to the input channels. The stuff-bits are removed and the reconstructed data signals are supplied to the output channels at the original bit rate. To provide the clock frequency necessary to reproduce the original bit rate, a tracking clock generator is used.
Asynchronous high speed over-sampling multiplexer-demultiplexer systems operate on the principle of a high speed commutator and decommutator. The data signals are multiplex sampled by an electronic commutator at a rate 10 times or more higher than the highest bit rate of the data signals. An electronic decommutator is synchronized to the commutator to allow one-to-one correspondence between the multiplexed data channels and demultiplexed data channels.
It should be noted that a data channel in a synchronous multiplexer-demultiplexer system can be used as an asynchronous high speed over-sampling channel provided the bit rate of the data signal is approximately 1/10 or lower than the specified operational bit rate of the data channel.
Most synchronous multiplexer-demultiplexer systems cannot accommodate the wide range of data bit rates required in facilities such as intelligent buildings because of the fixed operational bit rates of the data channels.
If the data channels are used as asynchronous high speed over-sampling data channels, the cost-effectiveness of the system obviously suffers because of the inefficient use of the overall transmission capacity.
Reconfiguring a synchronous multiplexer-demultiplexer system to accommodate a change in the operational bit rate of a data channel and/or the number of data channels involves a major modification in the system, or, in most cases, a complete replacement of the system. The cost of such reconfigurations are prohibitive.
The same can be said of most asynchronous multiplexer-demultiplexer systems.
Asynchronous high speed over-sampling multiplexer-demultiplexer systems cannot have many high bit rate data channels because the operational bit rate will readily exceed 100 Mb/s. Such bit rates require high cost ECL and GaAs integrated circuits, and cost effectiveness of the system is significantly diminished.
Ideally, a multiplexer-demultiplexer system for a facility such as an intelligent building should support bit rates ranging from DC contact closures to above 10 Mb/s for LANs (Local Area Networks) such as the Ethernet.